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Nanoscale plasmonic gaps are useful structures both electrically, for creating quantum tunnel junctions, and optically, for confining light. Inelastic tunneling of electrons in a tunnel junction is an attractive source of light due to the ultrafast response rate granted by the tunneling time of electrons in the system as well as the compact dimensions. A main hurdle for these light emitting tunnel junctions, however, is their low external efficiency given by both low electron-to-plasmon conversion as well as low plasmon-to-photon conversion. Inversely, coupling light into a nanogap for high confinement and field enhancement can be difficult due to the size mismatches involved. We show a 3 nm gap metal-insulator-metal plasmonic tunnel junction evanescently coupled to the fundamental TE mode of a standard silicon waveguide in a tapered directional coupler configuration with a transmission efficiency of 54.8% atλ =1.55μm and a 3-dB coupling bandwidth of 705 nm. In the inverse configuration, we show an electric field enhancement of |E|/|E₀| ≈120 within a plasmonic tunnel junction in the technologically important optical telecommunications band. 

Abstract Processing information in the optical domain promises advantages in both speed and energy efficiency over existing digital hardware for a variety of emerging applications in artificial intelligence and machine learning. A typical approach to photonic processing is to multiply a rapidly changing optical input vector with a matrix of fixed optical weights. However, encoding these weights on-chip using an array of photonic memory cells is currently limited by a wide range of material- and device-level issues, such as the programming speed, extinction ratio and endurance, among others. Here we propose a new approach to encoding optical weights for in-memory photonic computing using magneto-optic memory cells comprising heterogeneously integrated cerium-substituted yttrium iron garnet (Ce:YIG) on silicon micro-ring resonators. We show that leveraging the non-reciprocal phase shift in such magneto-optic materials offers several key advantages over existing architectures, providing a fast (1 ns), efficient (143 fJ per bit) and robust (2.4 billion programming cycles) platform for on-chip optical processing. 

The integration of computing with memory is essential for distributed, massively parallel, and adaptive architectures such as neural networks in artificial intelligence (AI). Accelerating AI can be achieved through photonic computing, but it requires nonvolatile photonic memory capable of rapid updates during on-chip training sessions or when new information becomes available during deployment. Phase-change materials (PCMs) are promising for providing compact, nonvolatile optical weighting; however, they face limitations in terms of bit precision, programming speed, and cycling endurance. Here, we propose a novel photonic memory cell that merges nonvolatile photonic weighting using PCMs with high-speed, volatile tuning enabled by an integrated PN junction. Our experiments demonstrate that the same PN modulator, fabricated via a foundry-compatible process, can achieve dual functionality. It supports coarse programmability for setting initial optical weights and facilitates high-speed fine-tuning to adjust these weights dynamically. The result shows a 400-fold increase in volatile tuning speed and a 10,000-fold enhancement in efficiency. This multifunctional photonic memory with volatile and nonvolatile capabilities could significantly advance the performance and versatility of photonic memory cells, providing robust solutions for dynamic computing environments. 

This paper presents \textit{OFHE}, an electro-optical accelerator designed to process Discretized TFHE (DTFHE) operations, which encrypt multi-bit messages and support homomorphic multiplications, lookup table operations and full-domain functional bootstrappings. While DTFHE is more efficient and versatile than other fully homomorphic encryption schemes, it requires 32-, 64-, and 128-bit polynomial multiplications, which can be time-consuming. Existing TFHE accelerators are not easily upgradable to support DTFHE operations due to limited datapaths, a lack of datapath bit-width reconfigurability, and power inefficiencies when processing FFT and inverse FFT (IFFT) kernels. Compared to prior TFHE accelerators, OFHE addresses these challenges by improving the DTFHE operation latency by 8.7\%, the DTFHE operation throughput by $$57\%$$, and the DTFHE operation throughput per Watt by $$94\%$$. 

Abstract Nonvolatile photonic integrated circuits employing phase change materials have relied either on optical switching mechanisms with precise multi-level control but poor scalability or electrical switching with seamless integration and scalability but mostly limited to a binary response. Recent works have demonstrated electrical multi-level switching; however, they relied on the stochastic nucleation process to achieve partial crystallization with low demonstrated repeatability and cyclability. Here, we re-engineer waveguide-integrated microheaters to achieve precise spatial control of the temperature profile (i.e., hotspot) and, thus, switch deterministic areas of an embedded phase change material cell. We experimentally demonstrate this concept using a variety of foundry-processed doped-silicon microheaters on a silicon-on-insulator platform to trigger multi-step amorphization and reversible switching of Sb₂Se₃and Ge₂Sb₂Se₄Te alloys. We further characterize the response of our microheaters using Transient Thermoreflectance Imaging. Our approach combines the deterministic control resulting from a spatially resolved glassy-crystalline distribution with the scalability of electro-thermal switching devices, thus paving the way to reliable multi-level switching towards robust reprogrammable phase-change photonic devices for analog processing and computing. 

We experimentally demonstrate the first electrically programmable, non-volatile silicon photonic content addressable memory cell using Sb₂Se₃phase change material on microring resonators, opening the path for light-based search operations in zero-power look-up tables. 

In this paper, we present AnalogVNN, a simulation framework built on PyTorch that can simulate the effects of optoelectronic noise, limited precision, and signal normalization present in photonic neural network accelerators. We use this framework to train and optimize linear and convolutional neural networks with up to nine layers and ∼1.7 × 106 parameters, while gaining insights into how normalization, activation function, reduced precision, and noise influence accuracy in analog photonic neural networks. By following the same layer structure design present in PyTorch, the AnalogVNN framework allows users to convert most digital neural network models to their analog counterparts with just a few lines of code, taking full advantage of the open-source optimization, deep learning, and GPU acceleration libraries available through PyTorch.